We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 6 Manufacturers, Suppliers and Companies | IPROS GMS

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. メディアリンクスエルエスアイラボ Kanagawa//Electronic Components and Semiconductors
  3. ナセル Tokyo//Industrial Electrical Equipment
  4. 4 Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  5. 4 大韓貿易投資振興公社(KOTRA) Tokyo//Government
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IP Cores Product ranking

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. IP core "AndesCore NX25F" 富士ソフト インダストリービジネス事業部
  2. IP Core 'IP_SMPTE2022_Video' メディアリンクスエルエスアイラボ
  3. IP Core Catalog Euresys Japan ユレシス　ジャパン
  4. IP core "AndesCore N10" 富士ソフト インダストリービジネス事業部
  5. 4 Aerospace HOLT Corporation 1553 IP Core Demo Kit ナセル

IP Cores Product List

1～28 item / All 28 items

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LDPC IP core

LDPC IP core

We provide a total solution for LDPC codes, from system design and computer simulation evaluation to IP macros.

LDPC (Low Density Parity Check) symbols LDPC symbols have error correction capabilities that are extremely close to the Shannon limit, and they are error correction codes that enable high-speed processing of codes through parallel processing. Features of Mobile Tech's LDPC Symbol Total Solution We provide Encoder/Decoder IPs with optimal configurations based on the required performance (circuit scale/througput) that support standard LDPC codes as well as customer-specific LDPC codes, and we also design and support peripheral modules to maximize performance.

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IP Core Catalog

IP Core Catalog

Includes practical reference designs! A wide variety of lineups are available.

This catalog introduces the "IP cores" handled by Euresys Japan Co., Ltd. It includes various products such as the compact and customizable "GigE Vision IP core," the "USB3 Vision IP core" with practical reference designs, and the "CoaXPress IP core." Please use this for selecting products. 【Featured Products (partial)】 ■ CoaXPress-over-Fiber Bridge IP core ■ GigE Vision IP core ■ USB3 Vision IP core ■ CoaXPress IP core ■ IMX Pregius IP core, etc. *For more details, please refer to the PDF document or feel free to contact us.

  • Other production and development software and systems
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IP Core 'IP_SMPTE2059_SLV'

IP Core 'IP_SMPTE2059_SLV'

Compliant with SMPTE 2059-1/2! Hitless time synchronization is possible through line redundancy.

The "IP_SMPTE2059_SLV" is an IP core for slaves compliant with ST 2059-1/2. There are two types: the vPTPM (Master-Core) on the master side and the vPTPS (Slave-Core) on the slave side, which can be used individually, in multiples, or in combination. Additionally, it has ports for sending and receiving control packets from the MPU bus and is compatible with NMOS, among others. 【Features】 ■ Compliant with SMPTE 2059-1/2 ■ Counter output for PTS ■ 1PPS output ■ Serial output of time information ■ Capable of sending and receiving control packets using the MPU *For more details, please refer to the PDF documentation or feel free to contact us.

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IP Core "IP_SMPTE2110"

IP Core "IP_SMPTE2110"

The video format supports 4K/HD/SD! You can manage Ethernet statistics.

The "IP_SMPTE2110" is an IP core compliant with ST 2110-10/20/30/40. It comes in two types: vEGSV (Egress-Core) for the transmission side and vIGSV (Ingress-Core) for the reception side. They can be used individually, in multiples, or in combination. Additionally, the number of SDI channels and Ethernet ports can be freely combined. 【Features】 ■ Compliant with SMPTE 2110-10/20/30 ■ Supports video formats 4K/HD/SD ■ SMPTE 2022-7 (Hitless support) ■ Capable of supporting control in-channel communication ■ Compatible with IPv4 and IPv6 *For more details, please refer to the PDF document or feel free to contact us.

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[Siliconarts] Raytracing GPU IP

[Siliconarts] Raytracing GPU IP

The world's first real-time Ray tracing & Path tracing GPU IP.

A fabless company that owns raytracing GPU IP and is planning to develop artificial intelligence models and AI processors for edge devices as a new business. For chip development, basic logic design is conducted internally, while backend design is primarily carried out through foundry design houses. [RayCore MC] - MIMD-based low-power high-performance real-time raytracing & path tracking GPU - Achieves real-time low-power raytracing functionality.

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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP Core 'IP_SMPTE2022_Video'

IP Core 'IP_SMPTE2022_Video'

An IP core that addresses network packet loss and ordering!

The "IP_SMPTE2022_Video" is an IP core compliant with SMPTE2022-5/6/7. It can handle multiple port inputs or outputs of 20-bit parallel data for 3G/HD. Additionally, changes on the line side are possible. It can support 10GbE/25GbE/40GbE (10GbE×4)/100GbE (25GbE×4), among others. 【Features】 ■ Error correction function using FEC compliant with SMPTE2022-5-2007 ■ MAC/IP/UDP/RTP filtering ■ Support for both IPv4 and IPv6 ■ Capability to include ARP ■ Hitless support compliant with SMPTE2022-7 (Hitless compatible) *For more details, please download the PDF or feel free to contact us.

  • Software (middle, driver, security, etc.)
  • Other embedded systems (software and hardware)
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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore E8"

IP core "AndesCore E8"

FlashFetch improves performance while saving power!

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

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Aerospace HOLT Corporation 1553 IP Core Demo Kit

Aerospace HOLT Corporation 1553 IP Core Demo Kit

Support for integrating the Holt HI-6300 IP core into Vivado design and FPGA implementation.

In the aerospace industry, reliable data transmission is essential. Particularly in communication under harsh environments, the accuracy and stability of data become crucial. The HI-6300 IP core supports FPGA implementation and provides a solution to enhance the reliability of data transmission. This product demonstrates access to IP bus controller (BC), remote terminal (RT), and monitor (MT) functions using the Holt API library. 【Usage Scenarios】 - Data transmission in aerospace equipment - Development of communication systems using FPGA - Evaluation of the HI-6300 IP core 【Benefits of Implementation】 - Rapid integration into FPGA designs - Improved reliability of data transmission - Reduced development time

  • Development support tools (ICE, emulators, debuggers, etc.)
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IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N15/N15F"

IP core "AndesCore N15/N15F"

It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore D15/D15F"

IP core "AndesCore D15/D15F"

It comes with various configuration options such as MMU, cache, and local memory!

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N7"

IP core "AndesCore N7"

It is possible to reduce it to 12K gates! It serves as an ideal alternative to the 8051 and other 8-bit processor cores.

The "AndesCore N7" is an IP core that supports controllers requiring low power consumption, such as touch screens, storage, mobile devices, and sensors, as well as network connectivity needed for IoT devices. The ultra-low power consumption and small circuit size of the N7 are designed for SOC designs with performance constraints. FlashFetch technology can enhance the performance of latency-prone flash memory without additional power consumption. 【Specifications】 ■ Seamless transition from 8/16-bit MCUs to a complete 32-bit environment ■ Low power consumption to extend battery life ■ Small footprint with fewer gates and high code density ■ Speeding up Flash access and reducing power consumption with FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N8"

IP core "AndesCore N8"

Reduce memory usage and lower customers' silicon costs!

The "AndesCore N8" is an IP core that provides a long-term roadmap for customers requiring an upgrade path from 8-bit cores. With the ability to process both 16-bit and 32-bit instructions, it enables a reduction in the ROM size of program data. While being a computing platform comparable to an 8-bit controller, it achieves the performance of an advanced 32-bit processor. 【Specifications】 ■ Excellent overall performance ■ Vector interrupts for low-latency interrupt handling ■ Small footprint with fewer gates and high code density ■ Faster Flash access and power reduction through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

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IP core "D32PRO"

IP core "D32PRO"

To meet the power consumption and size requirements of embedded devices, we are developing alternatives based on ARM Cortex M0/M0+/M1/M3 as much as possible!

The "D32PRO" is an IP core for a 32-bit microcontroller based on the Harvard architecture. It supports dual and multi-core systems, making it suitable for embedded systems that require higher computational performance and system complexity by improving code density. It comes with various peripheral interfaces such as USB, SPI, LCD, HDLC, UART, Ethernet MAC, CAN, LIN, and RTC, allowing for easy system construction. 【Specifications (partial)】 ■ 32-bit Harvard architecture ■ Maximum performance of 1.52/2.67 DMIPS/MHz and 2.59 CoreMarks/MHz ■ Minimum ASIC gate area of 10.6k/6.8k ■ 15 32-bit general-purpose registers ■ ASIC silicon-proven architecture *For more details, please download the PDF (English version) or feel free to contact us.

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IP core "DQ80251"

IP core "DQ80251"

Completely automated test bench and a complete test set included!

The DQ80251 is an IP core for a 16-bit/32-bit embedded microcontroller that is 100% binary compatible with the 16-bit 80C251 and the 8-bit 80C51 microcontrollers. It features a built-in DoCD-JTAG on-chip debugger and supports debugging software from Keil DK251 and DoCD. The Dhrystone 2.1 benchmark program runs at 75 times the speed of the original 80C51 and 6 times the speed of the original 80C251 under the same frequency conditions. Furthermore, due to its high instruction efficiency, the size of the code compiled for SOURCE mode is approximately half that of the equivalent standard 8051 code. 【Specifications (partial)】 ■ 100% binary compatible with 80C251 ■ Implements BINARY and SOURCE modes ■ Most instructions execute in 1 clock cycle ■ Quad pipeline architecture allows operation at the same frequency, 75 times faster than the original 80C51 and 6 times faster than the 80C251 *For more details, please download the PDF (English version) or feel free to contact us.

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IP core "DQ8051CPU"

IP core "DQ8051CPU"

You can easily verify the package at each stage of the SoC design flow!

The "DQ8051CPU" is an IP core for a single-chip 8-bit embedded microcontroller designed to operate with both high-speed (on-chip) and low-speed (off-chip) memory. It is 100% binary compatible with the 8051 8-bit microcontroller and is specifically designed with a focus on performance-to-power consumption ratio, featuring an advanced Power Management Unit (PMU). Additionally, it includes a built-in DoCD-JTAG on-chip debugger and supports the Keil μVision development platform as well as standalone DoCD debugging software. 【Specifications (partial)】 ■ 100% compatibility with 8051 ■ Capable of executing 28.40 times faster than the original 80C51 at the same frequency due to a quad-pipeline architecture ■ Up to 26.721 VAX MIPS at 100MHz ■ 24 times faster multiplication ■ 12 times faster division *For more details, please download the PDF (English version) or feel free to contact us.

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